/*
 * Copyright (C) 2018 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2018-12-06 15:47:51
 *
 */

#ifndef TOP_DVFS_APB_H
#define TOP_DVFS_APB_H

#define CTL_BASE_TOP_DVFS_APB 0x322A0000

#define REG_TOP_DVFS_APB_DCDC_MM_FIX_VOLTAGE_CTRL                  ( CTL_BASE_TOP_DVFS_APB + 0x0000 )
#define REG_TOP_DVFS_APB_DCDC_MM_DVFS_WAIT_WINDOW_CFG              ( CTL_BASE_TOP_DVFS_APB + 0x0004 )
#define REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY_CFG0             ( CTL_BASE_TOP_DVFS_APB + 0x0008 )
#define REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY_CFG1             ( CTL_BASE_TOP_DVFS_APB + 0x000C )
#define REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY_CFG0           ( CTL_BASE_TOP_DVFS_APB + 0x0010 )
#define REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY_CFG1           ( CTL_BASE_TOP_DVFS_APB + 0x0014 )
#define REG_TOP_DVFS_APB_DCDC_MM_SW_DVFS_CTRL                      ( CTL_BASE_TOP_DVFS_APB + 0x0018 )
#define REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_JUDGE_BYPASS              ( CTL_BASE_TOP_DVFS_APB + 0x001C )
#define REG_TOP_DVFS_APB_DCDC_MM_DVFS_STATE_DBG                    ( CTL_BASE_TOP_DVFS_APB + 0x0020 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_FIX_VOLTAGE_CTRL               ( CTL_BASE_TOP_DVFS_APB + 0x0024 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_WAIT_WINDOW_CFG           ( CTL_BASE_TOP_DVFS_APB + 0x0028 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY_CFG0          ( CTL_BASE_TOP_DVFS_APB + 0x002C )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY_CFG1          ( CTL_BASE_TOP_DVFS_APB + 0x0030 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY_CFG0        ( CTL_BASE_TOP_DVFS_APB + 0x0034 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY_CFG1        ( CTL_BASE_TOP_DVFS_APB + 0x0038 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_CTRL                   ( CTL_BASE_TOP_DVFS_APB + 0x003C )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_JUDGE_BYPASS           ( CTL_BASE_TOP_DVFS_APB + 0x0040 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_STATE_DBG                 ( CTL_BASE_TOP_DVFS_APB + 0x0044 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_FIX_VOLTAGE_CTRL                ( CTL_BASE_TOP_DVFS_APB + 0x0048 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_WAIT_WINDOW_CFG            ( CTL_BASE_TOP_DVFS_APB + 0x004C )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG2           ( CTL_BASE_TOP_DVFS_APB + 0x0050 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG1           ( CTL_BASE_TOP_DVFS_APB + 0x0054 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG0           ( CTL_BASE_TOP_DVFS_APB + 0x0058 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG2         ( CTL_BASE_TOP_DVFS_APB + 0x005C )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG1         ( CTL_BASE_TOP_DVFS_APB + 0x0060 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG0         ( CTL_BASE_TOP_DVFS_APB + 0x0064 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_CTRL                    ( CTL_BASE_TOP_DVFS_APB + 0x0068 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_JUDGE_BYPASS            ( CTL_BASE_TOP_DVFS_APB + 0x006C )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_STATE_DBG                  ( CTL_BASE_TOP_DVFS_APB + 0x0070 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_FIX_VOLTAGE_CTRL                ( CTL_BASE_TOP_DVFS_APB + 0x0074 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_WAIT_WINDOW_CFG            ( CTL_BASE_TOP_DVFS_APB + 0x0078 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG2           ( CTL_BASE_TOP_DVFS_APB + 0x007C )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG1           ( CTL_BASE_TOP_DVFS_APB + 0x0080 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG0           ( CTL_BASE_TOP_DVFS_APB + 0x0084 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG2         ( CTL_BASE_TOP_DVFS_APB + 0x0088 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG1         ( CTL_BASE_TOP_DVFS_APB + 0x008C )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG0         ( CTL_BASE_TOP_DVFS_APB + 0x0090 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_SW_DVFS_CTRL                    ( CTL_BASE_TOP_DVFS_APB + 0x0094 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_JUDGE_BYPASS            ( CTL_BASE_TOP_DVFS_APB + 0x0098 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_DBG                  ( CTL_BASE_TOP_DVFS_APB + 0x009C )
#define REG_TOP_DVFS_APB_DCDC_STEP_TUNE_CFG                        ( CTL_BASE_TOP_DVFS_APB + 0x00A0 )
#define REG_TOP_DVFS_APB_TOP_DVFS_CLK_CTRL                         ( CTL_BASE_TOP_DVFS_APB + 0x00A4 )
#define REG_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL                      ( CTL_BASE_TOP_DVFS_APB + 0x00A8 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL                   ( CTL_BASE_TOP_DVFS_APB + 0x00AC )
#define REG_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL                    ( CTL_BASE_TOP_DVFS_APB + 0x00B0 )
#define REG_TOP_DVFS_APB_DCDC_MM_VOL_TUNE_UP_CFG                   ( CTL_BASE_TOP_DVFS_APB + 0x00B4 )
#define REG_TOP_DVFS_APB_DCDC_MM_VOL_TUNE_DOWN_CFG                 ( CTL_BASE_TOP_DVFS_APB + 0x00B8 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOL_TUNE_UP_CFG                ( CTL_BASE_TOP_DVFS_APB + 0x00BC )
#define REG_TOP_DVFS_APB_DCDC_MODEM_VOL_TUNE_DOWN_CFG              ( CTL_BASE_TOP_DVFS_APB + 0x00C0 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_UP_CFG0                ( CTL_BASE_TOP_DVFS_APB + 0x00C4 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_UP_CFG1                ( CTL_BASE_TOP_DVFS_APB + 0x00C8 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_DOWN_CFG0              ( CTL_BASE_TOP_DVFS_APB + 0x00CC )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_DOWN_CFG1              ( CTL_BASE_TOP_DVFS_APB + 0x00D0 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_UP_CFG0                ( CTL_BASE_TOP_DVFS_APB + 0x00D4 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_UP_CFG1                ( CTL_BASE_TOP_DVFS_APB + 0x00D8 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_DOWN_CFG0              ( CTL_BASE_TOP_DVFS_APB + 0x00DC )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_DOWN_CFG1              ( CTL_BASE_TOP_DVFS_APB + 0x00E0 )
#define REG_TOP_DVFS_APB_DCDC_MM_DVFS_VOLTAGE_VALUE0               ( CTL_BASE_TOP_DVFS_APB + 0x00E4 )
#define REG_TOP_DVFS_APB_DCDC_MM_DVFS_VOLTAGE_VALUE1               ( CTL_BASE_TOP_DVFS_APB + 0x00E8 )
#define REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_VOLTAGE_VALUE0            ( CTL_BASE_TOP_DVFS_APB + 0x00EC )
#define REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_VOLTAGE_VALUE1            ( CTL_BASE_TOP_DVFS_APB + 0x00F0 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE_VALUE0             ( CTL_BASE_TOP_DVFS_APB + 0x00F4 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE_VALUE1             ( CTL_BASE_TOP_DVFS_APB + 0x00F8 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE_VALUE2             ( CTL_BASE_TOP_DVFS_APB + 0x00FC )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE_VALUE0             ( CTL_BASE_TOP_DVFS_APB + 0x0100 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE_VALUE1             ( CTL_BASE_TOP_DVFS_APB + 0x0104 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE_VALUE2             ( CTL_BASE_TOP_DVFS_APB + 0x0108 )
#define REG_TOP_DVFS_APB_DCDC_CPU_STEP_TUNE_VOL                    ( CTL_BASE_TOP_DVFS_APB + 0x010C )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG3           ( CTL_BASE_TOP_DVFS_APB + 0x0110 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG3         ( CTL_BASE_TOP_DVFS_APB + 0x0114 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG3           ( CTL_BASE_TOP_DVFS_APB + 0x0118 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG3         ( CTL_BASE_TOP_DVFS_APB + 0x011C )
#define REG_TOP_DVFS_APB_DCDC_CPU1_TYPE_SEL_CFG                    ( CTL_BASE_TOP_DVFS_APB + 0x0120 )
#define REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_VOL_TUNE_UP_CFG          ( CTL_BASE_TOP_DVFS_APB + 0x0124 )
#define REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_VOL_TUNE_DOWN_CFG        ( CTL_BASE_TOP_DVFS_APB + 0x0128 )
#define REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_DVFS_VOLTAGE_VALUE0      ( CTL_BASE_TOP_DVFS_APB + 0x012C )
#define REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_DVFS_VOLTAGE_VALUE1      ( CTL_BASE_TOP_DVFS_APB + 0x0130 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_SW_DVFS_CTRL_ADI                ( CTL_BASE_TOP_DVFS_APB + 0x0134 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_SW_DVFS_CTRL_I2C                ( CTL_BASE_TOP_DVFS_APB + 0x0138 )
#define REG_TOP_DVFS_APB_DCDC_MM_DVFS_STATE_DBG1                   ( CTL_BASE_TOP_DVFS_APB + 0x013C )
#define REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_STATE_DBG1                ( CTL_BASE_TOP_DVFS_APB + 0x0140 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_STATE_DBG1                 ( CTL_BASE_TOP_DVFS_APB + 0x0144 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_DBG1                 ( CTL_BASE_TOP_DVFS_APB + 0x0148 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_DBG2                 ( CTL_BASE_TOP_DVFS_APB + 0x014C )
#define REG_TOP_DVFS_APB_SUBSYS_SW_DVFS_EN_CFG                     ( CTL_BASE_TOP_DVFS_APB + 0x0150 )
#define REG_TOP_DVFS_APB_WTLCP_DVFS_URGENCY_CFG                    ( CTL_BASE_TOP_DVFS_APB + 0x0154 )
#define REG_TOP_DVFS_APB_DCDC_DVFS_CNT_CFG                         ( CTL_BASE_TOP_DVFS_APB + 0x0158 )
#define REG_TOP_DVFS_APB_DCDC_MM_DVFS_CNT                          ( CTL_BASE_TOP_DVFS_APB + 0x015C )
#define REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_CNT                       ( CTL_BASE_TOP_DVFS_APB + 0x0160 )
#define REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_CNT                        ( CTL_BASE_TOP_DVFS_APB + 0x0164 )
#define REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_CNT                        ( CTL_BASE_TOP_DVFS_APB + 0x0168 )
#define REG_TOP_DVFS_APB_DVFS_IDLE_VOL_CFG                         ( CTL_BASE_TOP_DVFS_APB + 0x016C )
#define REG_TOP_DVFS_APB_SHARE_DCDC_CFG                            ( CTL_BASE_TOP_DVFS_APB + 0x0170 )
#define REG_TOP_DVFS_APB_DCDC_TOP_FIX_VOLTAGE_CTRL                 ( CTL_BASE_TOP_DVFS_APB + 0x0174 )
#define REG_TOP_DVFS_APB_DCDC_TOP_DVFS_WAIT_WINDOW_CFG             ( CTL_BASE_TOP_DVFS_APB + 0x0178 )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY_CFG0            ( CTL_BASE_TOP_DVFS_APB + 0x017C )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY_CFG1            ( CTL_BASE_TOP_DVFS_APB + 0x0180 )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY_CFG0          ( CTL_BASE_TOP_DVFS_APB + 0x0184 )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY_CFG1          ( CTL_BASE_TOP_DVFS_APB + 0x0188 )
#define REG_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_CTRL                     ( CTL_BASE_TOP_DVFS_APB + 0x018C )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_JUDGE_BYPASS             ( CTL_BASE_TOP_DVFS_APB + 0x0190 )
#define REG_TOP_DVFS_APB_DCDC_TOP_DVFS_STATE_DBG                   ( CTL_BASE_TOP_DVFS_APB + 0x0194 )
#define REG_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL                     ( CTL_BASE_TOP_DVFS_APB + 0x0198 )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOL_TUNE_UP_CFG                  ( CTL_BASE_TOP_DVFS_APB + 0x019C )
#define REG_TOP_DVFS_APB_DCDC_TOP_VOL_TUNE_DOWN_CFG                ( CTL_BASE_TOP_DVFS_APB + 0x01A0 )
#define REG_TOP_DVFS_APB_DCDC_TOP_DVFS_VOLTAGE_VALUE0              ( CTL_BASE_TOP_DVFS_APB + 0x01A4 )
#define REG_TOP_DVFS_APB_DCDC_TOP_DVFS_VOLTAGE_VALUE1              ( CTL_BASE_TOP_DVFS_APB + 0x01A8 )
#define REG_TOP_DVFS_APB_DCDC_TOP_DVFS_STATE_DBG1                  ( CTL_BASE_TOP_DVFS_APB + 0x01AC )
#define REG_TOP_DVFS_APB_DCDC_TOP_DVFS_CNT                         ( CTL_BASE_TOP_DVFS_APB + 0x01B0 )
#define REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG0                ( CTL_BASE_TOP_DVFS_APB + 0x01C0 )
#define REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG1                ( CTL_BASE_TOP_DVFS_APB + 0x01C4 )
#define REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG2                ( CTL_BASE_TOP_DVFS_APB + 0x01C8 )
#define REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG3                ( CTL_BASE_TOP_DVFS_APB + 0x01CC )

/* REG_TOP_DVFS_APB_DCDC_MM_FIX_VOLTAGE_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_MM_FIX_VOLTAGE(x)                (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_MM_FIX_VOLTAGE_EN                BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MM_DVFS_WAIT_WINDOW_CFG */

#define BIT_TOP_DVFS_APB_DCDC_MM_DVFS_UP_WINDOW(x)             (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MM_DVFS_DOWN_WINDOW(x)           (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY_BAK(x)       (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY2(x)          (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY1(x)          (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_DELAY0(x)          (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY_BAK(x)     (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY2(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY1(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_DELAY0(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MM_SW_DVFS_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_ACK                      BIT(21)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_TUNE_EN                    BIT(20)
#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_VOLTAGE_SW(x)            (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_MM_JUDGE_VOLTAGE_SW(x)           (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_REQ_SW                   BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MM_VOLTAGE_JUDGE_BYPASS */

#define BIT_TOP_DVFS_APB_REG_AUDCP_SYS_VOLTAGE_MEET_BYP        BIT(2)
#define BIT_TOP_DVFS_APB_REG_GPU_TOP_VOLTAGE_MEET_BYP          BIT(1)
#define BIT_TOP_DVFS_APB_REG_MM_SYS_VOLTAGE_MEET_BYP           BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MM_DVFS_STATE_DBG */

#define BIT_TOP_DVFS_APB_DCDC_MM_JUDGE_VOLTAGE(x)              (((x) & 0x7) << 23)
#define BIT_TOP_DVFS_APB_DCDC_MM_CURRENT_VOLTAGE(x)            (((x) & 0x7) << 20)
#define BIT_TOP_DVFS_APB_DCDC_MM_DVFS_CNT(x)                   (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_MM_DVFS_STATE(x)                 (((x) & 0xF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_FIX_VOLTAGE_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_FIX_VOLTAGE(x)             (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_FIX_VOLTAGE_EN             BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_WAIT_WINDOW_CFG */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_DVFS_UP_WINDOW(x)          (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_DVFS_DOWN_WINDOW(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY_BAK(x)    (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY2(x)       (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY1(x)       (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_DELAY0(x)       (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY_BAK(x)  (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY2(x)     (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY1(x)     (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_DELAY0(x)     (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_ACK                   BIT(21)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_TUNE_EN                 BIT(20)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_VOLTAGE_SW(x)         (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_JUDGE_VOLTAGE_SW(x)        (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_REQ_SW                BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_JUDGE_BYPASS */

#define BIT_TOP_DVFS_APB_REG_AP_SYS_VOLTAGE_MEET_BYP           BIT(2)
#define BIT_TOP_DVFS_APB_REG_PUBCP_SYS_VOLTAGE_MEET_BYP        BIT(1)
#define BIT_TOP_DVFS_APB_REG_WTLCP_SYS_VOLTAGE_MEET_BYP        BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_STATE_DBG */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_JUDGE_VOLTAGE(x)           (((x) & 0x7) << 23)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_CURRENT_VOLTAGE(x)         (((x) & 0x7) << 20)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_DVFS_CNT(x)                (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_DVFS_STATE(x)              (((x) & 0xF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_FIX_VOLTAGE_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_FIX_VOLTAGE(x)              (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_FIX_VOLTAGE_EN              BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_WAIT_WINDOW_CFG */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_DVFS_UP_WINDOW(x)           (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_DVFS_DOWN_WINDOW(x)         (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY5(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY4(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY3(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY2(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY1(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY0(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY5(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY4(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY3(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY2(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY1(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY0(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_ACK                    BIT(21)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_TUNE_EN                  BIT(20)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_VOLTAGE_SW(x)          (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_JUDGE_VOLTAGE_SW(x)         (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_REQ_SW                 BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_JUDGE_BYPASS */

#define BIT_TOP_DVFS_APB_REG_APCPU_TOP_VOLTAGE_MEET_BYP        BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_STATE_DBG */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_JUDGE_VOLTAGE(x)            (((x) & 0x7) << 23)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_CURRENT_VOLTAGE(x)          (((x) & 0x7) << 20)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_DVFS_CNT(x)                 (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_DVFS_STATE(x)               (((x) & 0xF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_FIX_VOLTAGE_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_FIX_VOLTAGE(x)              (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_FIX_VOLTAGE_EN              BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_WAIT_WINDOW_CFG */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_DVFS_UP_WINDOW(x)           (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_DVFS_DOWN_WINDOW(x)         (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY5(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY4(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY3(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY2(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY1(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY0(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY5(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY4(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY3(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY2(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY1(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY0(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_SW_DVFS_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_SW_TUNE_EN                  BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_JUDGE_BYPASS */

#define BIT_TOP_DVFS_APB_REG_PROMETHEUS_VOLTAGE_MEET_BYP       BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_DBG */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_JUDGE_VOLTAGE(x)            (((x) & 0x7) << 28)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_CURRENT_VOLTAGE(x)          (((x) & 0x7) << 25)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_DVFS_CNT(x)                 (((x) & 0xFFFF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_I2C(x)           (((x) & 0x1F) << 4)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_ADI(x)           (((x) & 0xF))

/* REG_TOP_DVFS_APB_DCDC_STEP_TUNE_CFG */

#define BIT_TOP_DVFS_APB_DCDC_TOP_STEP_TUNE_EN                 BIT(4)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_STEP_TUNE_EN                BIT(3)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_STEP_TUNE_EN                BIT(2)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_STEP_TUNE_EN               BIT(1)
#define BIT_TOP_DVFS_APB_DCDC_MM_STEP_TUNE_EN                  BIT(0)

/* REG_TOP_DVFS_APB_TOP_DVFS_CLK_CTRL */

#define BIT_TOP_DVFS_APB_TOP_DVFS_AUTO_SEL_RCO_EN              BIT(2)
#define BIT_TOP_DVFS_APB_CGM_TOP_DVFS_FORCE_EN                 BIT(1)
#define BIT_TOP_DVFS_APB_CGM_TOP_DVFS_AUTO_GATE_SEL            BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL */

#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL7(x)              (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL6(x)              (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL5(x)              (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL4(x)              (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL3(x)              (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL2(x)              (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL1(x)              (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_MM_SW_DVFS_POLL0(x)              (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL7(x)           (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL6(x)           (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL5(x)           (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL4(x)           (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL3(x)           (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL2(x)           (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL1(x)           (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_SW_DVFS_POLL0(x)           (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL7(x)            (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL6(x)            (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL5(x)            (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL4(x)            (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL3(x)            (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL2(x)            (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL1(x)            (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_SW_DVFS_POLL0(x)            (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_MM_VOL_TUNE_UP_CFG */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_CFG_BAK(x)         (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_CFG2(x)            (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_CFG1(x)            (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_UP_CFG0(x)            (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_MM_VOL_TUNE_DOWN_CFG */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_CFG_BAK(x)       (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_CFG2(x)          (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_CFG1(x)          (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_DOWN_CFG0(x)          (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOL_TUNE_UP_CFG */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_CFG_BAK(x)      (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_CFG2(x)         (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_CFG1(x)         (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_UP_CFG0(x)         (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_MODEM_VOL_TUNE_DOWN_CFG */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_CFG_BAK(x)    (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_CFG2(x)       (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_CFG1(x)       (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_DOWN_CFG0(x)       (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_UP_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG3(x)          (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG2(x)          (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG1(x)          (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG0(x)          (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_UP_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG7(x)          (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG6(x)          (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG5(x)          (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_CFG4(x)          (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_DOWN_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG3(x)        (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG2(x)        (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG1(x)        (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG0(x)        (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOL_TUNE_DOWN_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG7(x)        (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG6(x)        (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG5(x)        (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_CFG4(x)        (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_UP_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG3_ADI(x)      (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG2_ADI(x)      (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG1_ADI(x)      (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG0_ADI(x)      (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_UP_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG7_ADI(x)      (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG6_ADI(x)      (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG5_ADI(x)      (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG4_ADI(x)      (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_DOWN_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG3_ADI(x)    (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG2_ADI(x)    (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG1_ADI(x)    (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG0_ADI(x)    (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOL_TUNE_DOWN_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG7_ADI(x)    (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG6_ADI(x)    (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG5_ADI(x)    (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG4_ADI(x)    (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_MM_DVFS_VOLTAGE_VALUE0 */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE2(x)                   (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE1(x)                   (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE0(x)                   (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_MM_DVFS_VOLTAGE_VALUE1 */

#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE_BAK(x)                (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOLTAGE3(x)                   (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_VOLTAGE_VALUE0 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE2(x)                (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE1(x)                (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE0(x)                (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_VOLTAGE_VALUE1 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE_BAK(x)             (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOLTAGE3(x)                (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE_VALUE0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE2(x)                 (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE1(x)                 (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE0(x)                 (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE_VALUE1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE5(x)                 (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE4(x)                 (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE3(x)                 (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE_VALUE2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE7(x)                 (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE6(x)                 (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE_VALUE0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE2_ADI(x)             (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE1_ADI(x)             (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE0_ADI(x)             (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE_VALUE1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE5_ADI(x)             (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE4_ADI(x)             (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE3_ADI(x)             (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE_VALUE2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE7_ADI(x)             (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE6_ADI(x)             (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_CPU_STEP_TUNE_VOL */

#define BIT_TOP_DVFS_APB_DCDC_TOP_STEP_VOLTAGE(x)              (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_MM_STEP_VOLTAGE(x)               (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_STEP_VOLTAGE(x)            (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_STEP_VOLTAGE(x)             (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_STEP_VOLTAGE(x)             (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY_CFG3 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY7(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_UP_DELAY6(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY_CFG3 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY7(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOLTAGE_DOWN_DELAY6(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY_CFG3 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY7(x)        (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_DELAY6(x)        (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY_CFG3 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY7(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_DELAY6(x)      (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_TYPE_SEL_CFG */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_DIALOG_EN                   BIT(0)

/* REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_VOL_TUNE_UP_CFG */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG7_I2C(x)      (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG6_I2C(x)      (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG5_I2C(x)      (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG4_I2C(x)      (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG3_I2C(x)      (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG2_I2C(x)      (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG1_I2C(x)      (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_UP_CFG0_I2C(x)      (((x) & 0x7))

/* REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_VOL_TUNE_DOWN_CFG */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG7_I2C(x)    (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG6_I2C(x)    (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG5_I2C(x)    (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG4_I2C(x)    (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG3_I2C(x)    (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG2_I2C(x)    (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG1_I2C(x)    (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE_DOWN_CFG0_I2C(x)    (((x) & 0x7))

/* REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_DVFS_VOLTAGE_VALUE0 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE3_I2C(x)             (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE2_I2C(x)             (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE1_I2C(x)             (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE0_I2C(x)             (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DIALOG_DCDC_CPU1_DVFS_VOLTAGE_VALUE1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE7_I2C(x)             (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE6_I2C(x)             (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE5_I2C(x)             (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOLTAGE4_I2C(x)             (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_CPU1_SW_DVFS_CTRL_ADI */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_ACK_ADI                BIT(20)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_VOLTAGE_SW_ADI(x)      (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_JUDGE_VOLTAGE_SW_ADI(x)     (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_REQ_SW_ADI             BIT(0)

/* REG_TOP_DVFS_APB_DCDC_CPU1_SW_DVFS_CTRL_I2C */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_ACK1_I2C               BIT(19)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_ACK0_I2C               BIT(18)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_JUDGE_VOLTAGE_SW_I2C(x)     (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_VOLTAGE_SW_I2C(x)      (((x) & 0x7F) << 8)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_REQ1_SW_I2C            BIT(7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_DOWN_CFG_SW_I2C(x)     (((x) & 0x7) << 4)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_UP_CFG_SW_I2C(x)       (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_REQ0_SW_I2C            BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MM_DVFS_STATE_DBG1 */

#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_VOLTAGE(x)               (((x) & 0xFFFF) << 15)
#define BIT_TOP_DVFS_APB_AUDCP_SYS_VOLTAGE_MEET                BIT(14)
#define BIT_TOP_DVFS_APB_GPU_SYS_VOLTAGE_MEET                  BIT(13)
#define BIT_TOP_DVFS_APB_MM_SYS_VOLTAGE_MEET                   BIT(12)
#define BIT_TOP_DVFS_APB_DCDC_MM_PRE_CURRENT_VOLTAGE(x)        (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MM_DVFS_VOLTAGE(x)               (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_MM_PRE_VOTE_VOLTAGE(x)           (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_MM_VOTE_VOLTAGE(x)               (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_STATE_DBG1 */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_VOLTAGE(x)            (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_AP_SYS_VOLTAGE_MEET                   BIT(14)
#define BIT_TOP_DVFS_APB_PUBCP_SYS_VOLTAGE_MEET                BIT(13)
#define BIT_TOP_DVFS_APB_WTLCP_SYS_VOLTAGE_MEET                BIT(12)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_PRE_CURRENT_VOLTAGE(x)     (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_DVFS_VOLTAGE(x)            (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_PRE_VOTE_VOLTAGE(x)        (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_VOTE_VOLTAGE(x)            (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_STATE_DBG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_VOLTAGE(x)             (((x) & 0xFFFF) << 13)
#define BIT_TOP_DVFS_APB_APCPU_TOP_VOLTAGE_MEET                BIT(12)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_PRE_CURRENT_VOLTAGE(x)      (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_DVFS_VOLTAGE(x)             (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_PRE_VOTE_VOLTAGE(x)         (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_VOTE_VOLTAGE(x)             (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_DBG1 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_VOLTAGE_ADI(x)         (((x) & 0xFFFF) << 13)
#define BIT_TOP_DVFS_APB_PROMETHUES_VOLTAGE_MEET               BIT(12)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_PRE_CURRENT_VOLTAGE(x)      (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_DVFS_VOLTAGE(x)             (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_PRE_VOTE_VOLTAGE(x)         (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_VOTE_VOLTAGE(x)             (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_STATE_DBG2 */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_CFG_I2C(x)             (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_VOLTAGE_I2C(x)         (((x) & 0x7F))

/* REG_TOP_DVFS_APB_SUBSYS_SW_DVFS_EN_CFG */

#define BIT_TOP_DVFS_APB_PUB_SW_DVFS_EN                        BIT(8)
#define BIT_TOP_DVFS_APB_APCPU_DCDC_CPU1_SW_DVFS_EN            BIT(7)
#define BIT_TOP_DVFS_APB_APCPU_DCDC_CPU0_SW_DVFS_EN            BIT(6)
#define BIT_TOP_DVFS_APB_AUDCP_SW_DVFS_EN                      BIT(5)
#define BIT_TOP_DVFS_APB_PUBCP_SW_DVFS_EN                      BIT(4)
#define BIT_TOP_DVFS_APB_WTLCP_SW_DVFS_EN                      BIT(3)
#define BIT_TOP_DVFS_APB_MM_SYS_SW_DVFS_EN                     BIT(2)
#define BIT_TOP_DVFS_APB_GPU_SYS_SW_DVFS_EN                    BIT(1)
#define BIT_TOP_DVFS_APB_AP_SYS_SW_DVFS_EN                     BIT(0)

/* REG_TOP_DVFS_APB_WTLCP_DVFS_URGENCY_CFG */

#define BIT_TOP_DVFS_APB_WTLCP_DVFS_URGENCY_EN                 BIT(0)

/* REG_TOP_DVFS_APB_DCDC_DVFS_CNT_CFG */

#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_CNT_CLR                 BIT(9)
#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_CNT_EN                  BIT(8)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_CNT_CLR                BIT(7)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_CNT_CLR                BIT(6)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_CNT_CLR               BIT(5)
#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_CNT_CLR                  BIT(4)
#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_CNT_EN                 BIT(3)
#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_CNT_EN                 BIT(2)
#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_CNT_EN                BIT(1)
#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_CNT_EN                   BIT(0)

/* REG_TOP_DVFS_APB_DCDC_MM_DVFS_CNT */

#define BIT_TOP_DVFS_APB_DCDC_MM_TUNE_CNT(x)                   (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_DCDC_MODEM_DVFS_CNT */

#define BIT_TOP_DVFS_APB_DCDC_MODEM_TUNE_CNT(x)                (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU0_DVFS_CNT */

#define BIT_TOP_DVFS_APB_DCDC_CPU0_TUNE_CNT(x)                 (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_DCDC_CPU1_DVFS_CNT */

#define BIT_TOP_DVFS_APB_DCDC_CPU1_TUNE_CNT(x)                 (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_DVFS_IDLE_VOL_CFG */

#define BIT_TOP_DVFS_APB_PUB_SYS_DVFS_IDLE_VOLTAGE(x)          (((x) & 0x7) << 27)
#define BIT_TOP_DVFS_APB_AUDCP_SYS_DVFS_IDLE_VOLTAGE(x)        (((x) & 0x7) << 24)
#define BIT_TOP_DVFS_APB_GPU_TOP_DVFS_IDLE_VOLTAGE(x)          (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_MM_SYS_DVFS_IDLE_VOLTAGE(x)           (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_WTLCP_SYS_DVFS_IDLE_VOLTAGE(x)        (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_PUBCP_SYS_DVFS_IDLE_VOLTAGE(x)        (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_AP_SYS_DVFS_IDLE_VOLTAGE(x)           (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_APCPU_TOP_DVFS_IDLE_VOLTAGE(x)        (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_PROMETHEUS_DVFS_IDLE_VOLTAGE(x)       (((x) & 0x7))

/* REG_TOP_DVFS_APB_SHARE_DCDC_CFG */

#define BIT_TOP_DVFS_APB_MM_MODEM_SHARE_DCDC_EN                BIT(0)

/* REG_TOP_DVFS_APB_DCDC_TOP_FIX_VOLTAGE_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_TOP_FIX_VOLTAGE(x)               (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_TOP_FIX_VOLTAGE_EN               BIT(0)

/* REG_TOP_DVFS_APB_DCDC_TOP_DVFS_WAIT_WINDOW_CFG */

#define BIT_TOP_DVFS_APB_DCDC_TOP_DVFS_UP_WINDOW(x)            (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_TOP_DVFS_DOWN_WINDOW(x)          (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY_BAK(x)      (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY2(x)         (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY1(x)         (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_DELAY0(x)         (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY_CFG0 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY_BAK(x)    (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY2(x)       (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY_CFG1 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY1(x)       (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_DELAY0(x)       (((x) & 0xFFFF))

/* REG_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_CTRL */

#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_ACK                     BIT(21)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_TUNE_EN                   BIT(20)
#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_VOLTAGE_SW(x)           (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_TOP_JUDGE_VOLTAGE_SW(x)          (((x) & 0x7) << 1)
#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_REQ_SW                  BIT(0)

/* REG_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_JUDGE_BYPASS */

#define BIT_TOP_DVFS_APB_REG_PUB_SYS_VOLTAGE_MEET_BYP          BIT(0)

/* REG_TOP_DVFS_APB_DCDC_TOP_DVFS_STATE_DBG */

#define BIT_TOP_DVFS_APB_DCDC_TOP_JUDGE_VOLTAGE(x)             (((x) & 0x7) << 23)
#define BIT_TOP_DVFS_APB_DCDC_TOP_CURRENT_VOLTAGE(x)           (((x) & 0x7) << 20)
#define BIT_TOP_DVFS_APB_DCDC_TOP_DVFS_CNT(x)                  (((x) & 0xFFFF) << 4)
#define BIT_TOP_DVFS_APB_DCDC_TOP_DVFS_STATE(x)                (((x) & 0xF))

/* REG_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL */

#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL7(x)             (((x) & 0x7) << 21)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL6(x)             (((x) & 0x7) << 18)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL5(x)             (((x) & 0x7) << 15)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL4(x)             (((x) & 0x7) << 12)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL3(x)             (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL2(x)             (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL1(x)             (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_TOP_SW_DVFS_POLL0(x)             (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_TOP_VOL_TUNE_UP_CFG */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_CFG_BAK(x)        (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_CFG2(x)           (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_CFG1(x)           (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_UP_CFG0(x)           (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_TOP_VOL_TUNE_DOWN_CFG */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_CFG_BAK(x)      (((x) & 0x7F) << 21)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_CFG2(x)         (((x) & 0x7F) << 14)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_CFG1(x)         (((x) & 0x7F) << 7)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_DOWN_CFG0(x)         (((x) & 0x7F))

/* REG_TOP_DVFS_APB_DCDC_TOP_DVFS_VOLTAGE_VALUE0 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE2(x)                  (((x) & 0x1FF) << 18)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE1(x)                  (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE0(x)                  (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_TOP_DVFS_VOLTAGE_VALUE1 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE_BAK(x)               (((x) & 0x1FF) << 9)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOLTAGE3(x)                  (((x) & 0x1FF))

/* REG_TOP_DVFS_APB_DCDC_TOP_DVFS_STATE_DBG1 */

#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_VOLTAGE(x)              (((x) & 0xFFFF) << 16)
#define BIT_TOP_DVFS_APB_PUB_SYS_VOLTAGE_MEET                  BIT(12)
#define BIT_TOP_DVFS_APB_DCDC_TOP_PRE_CURRENT_VOLTAGE(x)       (((x) & 0x7) << 9)
#define BIT_TOP_DVFS_APB_DCDC_TOP_DVFS_VOLTAGE(x)              (((x) & 0x7) << 6)
#define BIT_TOP_DVFS_APB_DCDC_TOP_PRE_VOTE_VOLTAGE(x)          (((x) & 0x7) << 3)
#define BIT_TOP_DVFS_APB_DCDC_TOP_VOTE_VOLTAGE(x)              (((x) & 0x7))

/* REG_TOP_DVFS_APB_DCDC_TOP_DVFS_CNT */

#define BIT_TOP_DVFS_APB_DCDC_TOP_TUNE_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG0 */

#define BIT_TOP_DVFS_APB_DVFS_RES_REG0(x)                      (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG1 */

#define BIT_TOP_DVFS_APB_DVFS_RES_REG1(x)                      (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG2 */

#define BIT_TOP_DVFS_APB_DVFS_RES_REG2(x)                      (((x) & 0xFFFFFFFF))

/* REG_TOP_DVFS_APB_TOP_DVFS_RESERVED_REG_CFG3 */

#define BIT_TOP_DVFS_APB_DVFS_RES_REG3(x)                      (((x) & 0xFFFFFFFF))

#endif